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"Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor."
Brian Zimmer et al. (2016)
- Brian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic:
Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. A-SSCC 2016: 121-124
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