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"Diagnosis of Transistor Shorts in Logic Test Environment."

Yoshinobu Higami et al. (2006)

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DOI: 10.1109/ATS.2006.260955

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-07

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Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, Yuzo Takamatsu:
Diagnosis of Transistor Shorts in Logic Test Environment. ATS 2006: 354-359

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