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"Synthesis optimization by redesigning FPGA architecture for area-speed ..."

R. Uma, P. Dhavachelvan (2012)

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DOI: 10.1145/2393216.2393271

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/ccseit/UmaD12b
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  - https://dblp.org/rec/conf/ccseit/UmaD12b
R. Uma, P. Dhavachelvan:
Synthesis optimization by redesigning FPGA architecture for area-speed optimization. CCSEIT 2012: 322-327

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