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"Performance optimization in flip flop circuit design."

Himadri Nath Saha et al. (2018)

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DOI: 10.1109/CCWC.2018.8301779

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-27

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  dblp key:
  - conf/ccwc/NathSahaJCDGKMC18
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  - https://dblp.org/rec/conf/ccwc/NathSahaJCDGKMC18
Himadri Nath Saha, Pooja Joshi, Adriza Chattopadhyay, Barsha Deb, Anurupa Ghosh, Puja Kumari, Dipak Kumar Mahato, Sayantani Choudhuri, Sayani Bhattacharjee, Sourav Chattopadhyay, Pranami Dash, Basab BijoyGharai:
Performance optimization in flip flop circuit design. CCWC 2018: 421-423

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