Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted ..."

Vineet Agrawal et al. (2013)

> Home

Details and statistics

DOI: 10.1109/CICC.2013.6658514

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/cicc/AgrawalKKKLBZRRWCRHEMTYMW13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/cicc/AgrawalKKKLBZRRWCRHEMTYMW13
Vineet Agrawal, N. Kepler, David Kidd, Gokul Krishnan, Samuel Leshner, T. Bakishev, D. Zhao, P. Ranade, R. Roy, M. Wojko, Lawrence T. Clark, Robert Rogenmoser, M. Hori, Taiji Ema, S. Moriwaki, T. Tsuruta, T. Yamada, J. Mitani, S. Wakayama:
Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. CICC 2013: 1-4

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.