"A 0.010mm2 9.92psrms low tracking jitter pixel clock generator ..."

Kangyeop Choo et al. (2014)

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DOI: 10.1109/CICC.2014.6946005

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Kangyeop Choo, Sung-Jin Kim, Wooseok Kim, Jihyun F. Kim, Taeik Kim, Hojin Park:
A 0.010mm² 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. CICC 2014: 1-4

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