"A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with ..."

Ming-Zhang Kuo et al. (2013)

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DOI: 10.1109/CICC.2013.6658452

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-17

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Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong:
A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm² per MB. CICC 2013: 1-4

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