"Dynamic, multi-core cache coherence architecture for power-sensitive ..."

Garo Bournoutian, Alex Orailoglu (2011)

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DOI: 10.1145/2039370.2039387

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Garo Bournoutian, Alex Orailoglu:
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors. CODES+ISSS 2011: 89-98

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