"Design of Multi-phase Clock Generation and Selection Circuit for CDR."

Junyong Deng, Lin Jiang, Zecang Zeng (2009)

> Home

Details and statistics

DOI: 10.1109/CSIE.2009.459

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/csie/DengJZ09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/csie/DengJZ09
Junyong Deng, Lin Jiang, Zecang Zeng:
Design of Multi-phase Clock Generation and Selection Circuit for CDR. CSIE (3) 2009: 387-391

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.