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"Challenges in gate level modeling for delay and SI at 65nm and below."

Igor Keller, King Ho Tam, Vinod Kariat (2008)

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DOI: 10.1145/1391469.1391590

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/dac/KellerTK08
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  - https://dblp.org/rec/conf/dac/KellerTK08
Igor Keller, King Ho Tam, Vinod Kariat:
Challenges in gate level modeling for delay and SI at 65nm and below. DAC 2008: 468-473

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