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"Transistor level gate modeling for accurate and fast timing, noise, and ..."

S. Raja et al. (2008)

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DOI: 10.1145/1391469.1391588

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  - conf/dac/RajaVBG08
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S. Raja, F. Varadi, Murat R. Becer, Joao Geada:
Transistor level gate modeling for accurate and fast timing, noise, and power analysis. DAC 2008: 456-461

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