"VHDL & Verilog Compared & Contrasted - Plus Modeled Example ..."

Douglas J. Smith (1996)

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DOI: 10.1145/240518.240664

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Douglas J. Smith:
VHDL & Verilog Compared & Contrasted - Plus Modeled Example Written in VHDL, Verilog and C. DAC 1996: 771-776

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