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"System and circuit level power modeling of energy-efficient 3D-stacked ..."

Karthik Chandrasekar et al. (2013)

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DOI: 10.7873/DATE.2013.061

access: closed

type: Conference or Workshop Paper

metadata version: 2021-07-25

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  dblp key:
  - conf/date/0001WAWG13
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  persistent URL:
  - https://dblp.org/rec/conf/date/0001WAWG13
Karthik Chandrasekar, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs. DATE 2013: 236-241

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