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"A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Thomas Froehlich, Vivek Sharma, Markus Bingesser (2010)

Dagstuhl

Trier

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DOI: 10.1109/DATE.2010.5457109

access: closed

type: Conference or Workshop Paper

metadata version: 2020-11-27

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Thomas Froehlich, Vivek Sharma, Markus Bingesser:
A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR. DATE 2010: 706-710

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last updated on 2020-11-27 14:57 CET by the dblp team

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