"Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime."

Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang (2019)

> Home

Details and statistics

DOI: 10.1109/DDECS.2019.8724660

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ddecs/ChenCH19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ddecs/ChenCH19
Kai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang:
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime. DDECS 2019: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.