"A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage ..."

Xiang Zheng et al. (2012)

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DOI: 10.1109/DDECS.2012.6219052

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Xiang Zheng, Ming Liu, Hong Chen, Huamin Cao, Cong Wang, Zhiqiang Gao:
A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique. DDECS 2012: 191-192

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