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"How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip ..."
Matthias Függer, Andreas Dielacher, Ulrich Schmid (2010)
- Matthias Függer, Andreas Dielacher, Ulrich Schmid:
How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining. EDCC 2010: 230-239
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