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"Designing ultra-low voltage PLL Using a bulk-driven technique."

Ting-Sheng Chao et al. (2009)

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DOI: 10.1109/ESSCIRC.2009.5325983

access: closed

type: Conference or Workshop Paper

metadata version: 2020-07-07

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  - conf/esscirc/ChaoLYC09
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  - https://dblp.org/rec/conf/esscirc/ChaoLYC09
Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng:
Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC 2009: 388-391

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