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"On-chip leakage monitor circuit to scan optimal reverse bias voltage for ..."

Masako Fujii et al. (2008)

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DOI: 10.1109/ESSCIRC.2008.4681841

access: closed

type: Conference or Workshop Paper

metadata version: 2021-06-10

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  - conf/esscirc/FujiiSNMS08
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Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara:
On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. ESSCIRC 2008: 258-261

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