"A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz ..."

Cheng-Liang Hung et al. (2011)

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DOI: 10.1109/ESSCIRC.2011.6045003

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Cheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang:
A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generation. ESSCIRC 2011: 447-450

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