"Digital delay locked loop with open-loop digital duty cycle corrector for ..."

Chun-Seok Jeong et al. (2004)

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DOI: 10.1109/ESSCIR.2004.1356697

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-29

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Chun-Seok Jeong, Changsik Yoo, Jae-Jin Lee, Joongsik Kih:
Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM. ESSCIRC 2004: 379-382

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