"A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated ..."

Abhirup Lahiri et al. (2014)

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DOI: 10.1109/ESSCIRC.2014.6942028

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Abhirup Lahiri, Nitin Gupta, Anand Kumar, Pradeep Dhadda:
A 600µA 32 kHz input 960 MHz output CP-PLL with 530ps integrated jitter in 28nm FD-SOI process. ESSCIRC 2014: 87-90

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