"A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high ..."

Arnoud P. van der Wel, Gerrit den Besten (2011)

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DOI: 10.1109/ESSCIRC.2011.6044891

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Arnoud P. van der Wel, Gerrit den Besten:
A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOS. ESSCIRC 2011: 167-170

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