"A fault model for VHDL descriptions at the register transfer level."

Teresa Riesgo, Javier Uceda (1996)

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DOI: 10.1109/EURDAC.1996.558244

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Teresa Riesgo, Javier Uceda:
A fault model for VHDL descriptions at the register transfer level. EURO-DAC 1996: 462-467

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