"A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a ..."

Al Walters, Peter Athanas (1998)

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DOI: 10.1109/FPGA.1998.707941

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  persistent URL:
  - https://dblp.org/rec/conf/fccm/WaltersA98
Al Walters, Peter Athanas:
A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing Machine. FCCM 1998: 333-334

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