"Hybrid masking using intra-masking dual-rail memory on LUT for ..."

Anh-Tuan Hoang, Takeshi Fujino (2013)

> Home

Details and statistics

DOI: 10.1145/2435264.2435315

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/HoangF13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/HoangF13
Anh-Tuan Hoang, Takeshi Fujino:
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). FPGA 2013: 266-267

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.