"A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract)."

David Jefferson et al. (1998)

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DOI: 10.1145/275107.275148

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-22

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David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff:
A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). FPGA 1998: 256

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