"Buffer Placement and Sizing for High-Performance Dataflow Circuits."

Lana Josipovic et al. (2020)

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DOI: 10.1145/3373087.3375314

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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Lana Josipovic, Shabnam Sheikhha, Andrea Guerrieri, Paolo Ienne, Jordi Cortadella:
Buffer Placement and Sizing for High-Performance Dataflow Circuits. FPGA 2020: 186-196

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