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"A 475 MHz Manycore FPGA Accelerator for RTL Simulation."

Sahand Kashani et al. (2024)

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DOI: 10.1145/3626202.3637579

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-15

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  dblp key:
  - conf/fpga/KashaniEKPRL24
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  - https://dblp.org/rec/conf/fpga/KashaniEKPRL24
Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus:
A 475 MHz Manycore FPGA Accelerator for RTL Simulation. FPGA 2024: 78-84

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