"Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic ..."

Junzhong Shen et al. (2020)

> Home

Details and statistics

DOI: 10.1145/3373087.3375331

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/ShenWTZZ20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/ShenWTZZ20
Junzhong Shen, Mei Wen, Minjin Tang, Xiaolei Zhao, Chunyuan Zhang:
Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. FPGA 2020: 315

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.