"SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple ..."

Michael J. Wirthlin et al. (2016)

> Home

Details and statistics

DOI: 10.1145/2847263.2847278

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/WirthlinKMRLD16
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/WirthlinKMRLD16
Michael J. Wirthlin, Andrew M. Keller, Chase McCloskey, Parker Ridd, David S. Lee, Jeffrey Draper:
SEU Mitigation and Validation of the LEON3 Soft Processor Using Triple Modular Redundancy for Space Processing. FPGA 2016: 205-214

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.