"Bit-level optimization for high-level synthesis and FPGA-based acceleration."

Jiyu Zhang et al. (2010)

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DOI: 10.1145/1723112.1723124

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong:
Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA 2010: 59-68

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