"Reducing FPGA Router Run-Time through Algorithm and Architecture."

Marcel Gort, Jason Helge Anderson (2011)

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DOI: 10.1109/FPL.2011.67

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  - https://dblp.org/rec/conf/fpl/GortA11
Marcel Gort, Jason Helge Anderson:
Reducing FPGA Router Run-Time through Algorithm and Architecture. FPL 2011: 336-342

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