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"A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density ..."

Yanni Chen, Dale E. Hocevar (2003)

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DOI: 10.1109/GLOCOM.2003.1258213

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Yanni Chen, Dale E. Hocevar:
A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder. GLOBECOM 2003: 113-117

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