"A design for concurrent error detections in FPLAs."

Tsin-Yuan Chang et al. (1992)

> Home

Details and statistics

DOI: 10.1109/GLSV.1992.218371

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/ChangHWL92
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/ChangHWL92
Tsin-Yuan Chang, Jean-Bean Hsu, Cheng-Chi Wang, Yu-Shen Lin:
A design for concurrent error detections in FPLAs. Great Lakes Symposium on VLSI 1992: 9-15

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.