"A design flow to optimize circuit delay by using standard cells and PLAs."

Rajesh Garg et al. (2006)

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DOI: 10.1145/1127908.1127960

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-20

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Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri:
A design flow to optimize circuit delay by using standard cells and PLAs. ACM Great Lakes Symposium on VLSI 2006: 217-222

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