"Clock-Wirelength-Driven Detailed Placement."

Ziang Ge et al. (2025)

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DOI: 10.1145/3716368.3735165

access: closed

type: Conference or Workshop Paper

metadata version: 2025-06-30

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Ziang Ge, Yikai Liu, Jindong Zhou, Pingqiang Zhou:
Clock-Wirelength-Driven Detailed Placement. ACM Great Lakes Symposium on VLSI 2025: 413-419

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