"Instruction cache leakage reduction by changing register operands and ..."

Maziar Goudarzi, Tohru Ishihara (2008)

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DOI: 10.1145/1366110.1366201

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Maziar Goudarzi, Tohru Ishihara:
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells. ACM Great Lakes Symposium on VLSI 2008: 383-386

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