"On efficient generation of instruction sequences to test for delay defects ..."

Sankar Gurumurthy et al. (2008)

> Home

Details and statistics

DOI: 10.1145/1366110.1366178

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/GurumurthyVAN08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/GurumurthyVAN08
Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan:
On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI 2008: 279-284

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.