"Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect."

Zhenlin Pei et al. (2023)

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DOI: 10.1145/3583781.3590311

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Francky Catthoor, Zsolt Tokei, Chenyun Pan:
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. ACM Great Lakes Symposium on VLSI 2023: 159-162

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