"Generic sub-space algorithm for generating reduced order models of linear ..."

J. V. R. Ravindra, M. B. Srinivas (2008)

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DOI: 10.1145/1366110.1366138

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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J. V. R. Ravindra, M. B. Srinivas:
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits. ACM Great Lakes Symposium on VLSI 2008: 111-114

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