"FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline ..."

Chaolong Xu et al. (2024)

> Home

Details and statistics

DOI: 10.1145/3649476.3658741

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/XuLPXY24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/XuLPXY24
Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang:
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. ACM Great Lakes Symposium on VLSI 2024: 13-18

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.