"STEP: a unified design methodology for secure test and IP core protection."

Pranav Yeolekar et al. (2012)

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DOI: 10.1145/2206781.2206862

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
STEP: a unified design methodology for secure test and IP core protection. ACM Great Lakes Symposium on VLSI 2012: 333-338

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