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"A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect ..."

Mu-Shan Lin et al. (2016)

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DOI: 10.1109/HOTCHIPS.2016.7936211

access: closed

type: Conference or Workshop Paper

metadata version: 2020-04-02

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  - conf/hotchips/LinTHHCYFZCLCKT16
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  - https://dblp.org/rec/conf/hotchips/LinTHHCYFZCLCKT16
Mu-Shan Lin, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh, Wen-Hung Huang, Yu-Chi Chen, Shu-Chun Yang, Chin-Ming Fu, Hao-Jie Zhan, Jinn-Yeh Chien, Shao-Yu Li, Y.-H. Chen, C.-C. Kuo, Shih-Peng Tai, Kazuyoshi Yamada:
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package. Hot Chips Symposium 2016: 1-32

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