
BibTeX record conf/hpca/SaileshwarNREQ18
@inproceedings{DBLP:conf/hpca/SaileshwarNREQ18, author = {Gururaj Saileshwar and Prashant J. Nair and Prakash Ramrakhyani and Wendy Elsasser and Moinuddin K. Qureshi}, title = {{SYNERGY:} Rethinking Secure-Memory Design for Error-Correcting Memories}, booktitle = {{IEEE} International Symposium on High Performance Computer Architecture, {HPCA} 2018, Vienna, Austria, February 24-28, 2018}, pages = {454--465}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/HPCA.2018.00046}, doi = {10.1109/HPCA.2018.00046}, timestamp = {Wed, 16 Oct 2019 14:14:50 +0200}, biburl = {https://dblp.org/rec/conf/hpca/SaileshwarNREQ18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }

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