"Design and implementation of high-performance master/slave memory ..."

Shashisekhar Ramagundam et al. (2014)

> Home

Details and statistics

DOI: 10.1109/I2MTC.2014.6860513

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/i2mtc/RamagundamDMBGA14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/i2mtc/RamagundamDMBGA14
Shashisekhar Ramagundam, Sunil R. Das, Scott Morton, Satyendra N. Biswas, Voicu Groza, Mansour H. Assaf, Emil M. Petriu:
Design and implementation of high-performance master/slave memory controller with microcontroller bus architecture. I2MTC 2014: 10-15

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.