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"Efficient design of full adder and subtractor using 5-input majority gate ..."
Ramanand Jaiswal, Trailokya Nath Sasamal (2017)
- Ramanand Jaiswal, Trailokya Nath Sasamal:
Efficient design of full adder and subtractor using 5-input majority gate in QCA. IC3 2017: 1-6
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