"Formal Verification for Logical Circuit Design Optimization in Computer ..."

Ashwini Kumar, Neeraj Sharma, Baishakhi Debnath (2024)

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DOI: 10.1109/ICCCNT61001.2024.10724132

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type: Conference or Workshop Paper

metadata version: 2025-06-30

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Ashwini Kumar, Neeraj Sharma, Baishakhi Debnath:
Formal Verification for Logical Circuit Design Optimization in Computer Architecture. ICCCNT 2024: 1-6

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