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"Logical Effort Analysis of various VLSI design algorithms."

Rommel M. Anacan, Josephine L. Bagay (2015)

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DOI: 10.1109/ICCSCE.2015.7482151

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - https://dblp.org/rec/conf/iccsce/AnacanB15
Rommel M. Anacan, Josephine L. Bagay:
Logical Effort Analysis of various VLSI design algorithms. ICCSCE 2015: 19-23

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