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"Scalable, high-speed on-chip-based NDN name forwarding using FPGA."

Divya Saxena et al. (2019)

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DOI: 10.1145/3288599.3288613

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

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  dblp key:
  - conf/icdcn/SaxenaMRC19
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  - https://dblp.org/rec/conf/icdcn/SaxenaMRC19
Divya Saxena, Suyash Mahar, Vaskar Raychoudhury, Jiannong Cao:
Scalable, high-speed on-chip-based NDN name forwarding using FPGA. ICDCN 2019: 81-89

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